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| 'DWD 6KHHW MUAA Routing Co-Processor (RCP) Family $33/,&$7,21 %(1(),76 * High-performance MAC Address processor for multiport switches and routers (up to 48 10/100Mb or 4 Gigabit Ethernet at wire speed) Layer 4 flow recognition for Quality of Service up to 16.7 million packets per second ARP cache manager/IP address caching at 12.5 million packets per second Synchronous interfaces and programmable priority between ports for simplicity of design Learn, age, and auto-age functions with "virtual queues" keeping track of aged and learned entries Transparent cascade of up to four devices without external logic, software setup, or performance hit ',67,1&7,9( &+$5$&7(5,67,&6 * * * * * 2K and 8K x 80-bit partitionable CAM/RAM data field in address database 32-bit synchronous port with separate inputs and outputs; optional 16-bit configuration 32-bit bi-directional processor port; optional 16-bit configuration Pipelined operation Operations performed from the synchronous port or processor port; all flags independently available to both ports 9-bit internal time stamp 50 MHz clock 160-pin PQFP package 3.3 Volt core with 3.3 Volt/5 Volt tolerant IO buffers IEEE 1149.1 (JTAG) compliant 6\Q. 3RUW ',1 * * * * * * * * * * 3UR.HVVRU 3RUW ',1 WR ELW PX[ WR ELW PX[ ',15($'< 23 ',1( ELW ODW.K ELW ODW.K ELW WR PX[ 352&' 352&$ 3&6 5: 352&5($'< ,17 5(6(7 &/. 3UR.HVVRU 3RUW '287 '2879$/,' '287( 2( &RQWURO $GGUHVV 'DWD %DVH ELW W EL )) 0) )ODJ DQG &KDLQ /RJL. &+$,1 &+$,183 &+$,1'1 &+$,1&6 ELW OD W.K ELW OD W.K WR ELW PX[ WR ELW PX[ 7', 706 7&. 7567 -7$* 7'2 )LJXUH %OR.N 'LDJUDP 086,& 6HPL.RQGX.WRUV WKH 086,& ORJR DQG WKH SKUDVH 086,& 6HPL.RQGX.WRUV DUH 5HJLVWHUHG WUDGHPDUNV RI 086,& 6HPL.RQGX.WRUV 086,& LV D WUDGHPDUN RI 086,& 6HPL.RQGX.WRUV 6\Q. 3RUW '287 2.WREHU 5HY 08$$ 5RXWLQJ &R3UR.HVVRU 5&3 )DPLO\ *HQHUDO 'HV.ULSWLRQ *(1(5$/ '(6&5,37,21 The MUSIC MUAA Routing Co-Processor (RCP) family consists of 80-bit wide content-addressable memories (CAMs), available in depths of 2K and 8K words. The CAM/RAM associated data partition is programmable from 32 bits of CAM and 48 bits of associated data, to 80 bits of CAM and 0 bits of RAM. The MUAA RCP can perform normal routing functions such as search, insert, and delete on single entries and can age multiple entries simultaneously. In addition, there is a learn instruction, particularly useful in networking applications. For maximum flexibility all the operations may be performed either through the processor port or through the synchronous port. Operations may occur on both ports simultaneously; the port with the highest priority will gain access first if both ports require a read or write into the CAM array simultaneously. The synchronous interface consists of 32-bit wide input and output ports, both of which may be configured as 16 bits. The data is multiplexed into and out of the CAM and RAM associated data field. Where input or output data is wider than the port, it is loaded or unloaded in multiple cycles starting with the least significant word. Internally the device is pipelined; once an operation is started on the synchronous port the next operation may be loaded and the results of the previous operation unloaded, thus maximizing device throughput. Multiple MUAA RCPs may be chained transparently to provide deeper memory. No software configuration is necessary. Each MUAA RCP detects where it is in the chain from the chaining pins on the previous device. A register is provided to inform the host of the total available CAM memory and the number of CAMs chained. All operations to the chained CAM are totally transparent. No individual device selection or addressing is required. The MUSIC MUAA RCP has aging, auto-aging, and learning functions. All entries have a 9-bit time stamp and may be marked as static to prevent the aging function from deleting them. When auto aging is enabled it may be configured to have higher or lower priority access than the ports. Two internal virtual queues of learned and aged entries are available. As entries are learned or aged out they are tagged as such and may be read from the device through either of the ports. This feature enables simple host management of aged out and learned entries. IEEE Standard. 1149.1 (JTAG) testability is implemented providing BYPASS, SAMPLE/PRELOAD, EXTEST, CLAMP, and HIGH-Z functions. 5HY 3LQ 'HV.ULSWLRQV 08$$ 5RXWLQJ &R3UR.HVVRU 5&3 )DPLO\ 3,1 '(6&5,37,216 Note: Signal names that start with a slash ("/") are active LOW. All signals are 3.3 Volt CMOS level. All input and bi-directional pins are 5-Volt tolerant, except for CLK. Never leave inputs floating except where indicated. The CAM architecture draws large currents during search operations, mandating the use of good layout and bypassing techniques. Refer to the Electrical Characteristics section for more information. VCC DOUT0 GND DIN31 DIN30 DIN29 DIN28 DIN27 GND DIN26 DIN25 DIN24 DIN23 DIN22 DIN21 VCC DIN20 DIN19 DIN18 DIN17 DIN16 DIN15 DIN14 GND DIN13 DIN12 DIN11 DIN10 DIN9 DIN8 DIN7 VCC DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 GND 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 GND DOUT1 DOUT2 DOUT3 DOUT4 VCC DOUT5 DOUT6 DOUT7 GND DOUT8 DOUT9 DOUT10 DOUT11 VCC DOUT12 DOUT13 DOUT14 DOUT15 GND DOUT16 DOUT17 DOUT18 DOUT19 VCC DOUT20 DOUT21 DOUT22 DOUT23 GND DOUT24 DOUT25 DOUT26 DOUT27 VCC DOUT28 DOUT29 DOUT30 DOUT31 GND 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 160-Pin PQFP 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VCC CHAINDN CHAINUP GND CHAIN3 CHAIN2 CHAIN1 CHAIN0 GND CHAINCS PROCD31 PROCD30 PROCD29 PROCD28 PROCD27 PROCD26 PROCD25 PROCD24 VCC PROCD23 PROCD22 PROCD21 PROCD20 PROCD19 PROCD18 GND PROCD17 PROCD16 PROCD15 PROCD14 PROCD13 PROCD12 VCC PROCD11 PROCD10 PROCD9 PROCD8 PROCD7 PROCD6 GND ',1>@ ,QSXW DIN[31:0] are synchronous port data input pins. Data is loaded into the MUAA RCP right aligned, least significant word first. ',1( ,QSXW DIN is sampled by the rising edge of CLK when /DINE is asserted. 5HY VCC CLK GND /MF /FF /DOUTVALID DINREADY INT PROCREADY TDO GND TDI TMS TCK /TRST /OE /DOUTE /DINE OP0 OP1 OP2 OP3 VCC PROCA0 PROCA1 PROCA2 PROCA3 PROCA4 PROCA5 R/W /PCS /RESET GND PROCD0 PROCD1 PROCD2 PROCD3 PROCD4 PROCD5 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 )LJXUH 3LQ 34)3 7RS 9LHZ 23>@ ,QSXW OP[3:0] is a synchronous port operation to be performed on the data applied to the DIN pins. OP is sampled by the rising edge of CLK when /DINE is asserted. When loading the CAM/RAM words to DIN, OP is set to LOAD except for the last word. OP for the last word is set to the desired operation. 08$$ 5RXWLQJ &R3UR.HVVRU 5&3 )DPLO\ ',15($'< 2XWSXW When DINREADY is HIGH, the synchronous port accepted the current operation. This is affected by the priority set for the DIN port and the processor port. Note, DINREADY may be LOW for up to 800 CLK periods after /RESET is taken HIGH. The JTAG interface is able to set DINREADY to HIGH-Z. Active HIGH. '287>@ 6WDWH 2XWSXW DOUT[31:0] is the synchronous port data output. Data is read out right aligned, least significant word first. The address index (bits 25-0), SWEX flag (bit 26), PWEX flag (bit 27), LQUEUE flag (bit 28), AQUEUE flag (bit 29), Sync Port Match flag (bit 30), and Full flag (bit 31) may also be read from this port before or after operation data depending on configuration. '2879$/,' 2XWSXW /DOUTVALID indicates when new data is available at the synchronous output port. /DOUTVALID is active LOW for one CLK cycle. /DOUTVALID may be configured to become active on the same clock as new DOUT becomes valid or the CLK before. The JTAG interface is able to set /DOUTVALID to HIGH-Z. 2( ,QSXW /OE is the DOUT High Impedance control. '287( ,QSXW /DOUTE is the DOUT enable control. When the DOUT data word is configured to be wider than the output port then this strobe enables the next word(s) of the DOUT data onto the DOUT pins. 352&'>@ %LGLUH.WLRQDO The bi-directional Processor data port provides the processor interface to the device. On write cycles, all devices respond in parallel. On read cycles, the appropriate device responds without additional intervention from the processor. 352&$>@ ,QSXW Processor port address bus. Selects which device register is accessed. Bit 0 is only used when the port is set to 16-bit mode, otherwise it should be held at a valid logic level. 5: ,QSXW R/W is the processor port read/write control pin. This pin is HIGH for reads, LOW for writes. 3&6 ,QSXW /PCS is the processor port chip select pin. When LOW this pin indicates a cycle to the processor port. On write cycles data must be set up to the rising edge of /PCS. On read 3LQ 'HV.ULSWLRQV cycles /PCS controls the output enable of the PROCD bus. Note that /PCS may be asynchronous to CLK. 352&5($'< 2XWSXW When PROCREADY is HIGH, indicates the processor read data is available or the processor write data is accepted. Priority may be set between the DIN port and the processor port. Note PROCREADY may be LOW for up to 800 CLK periods after /RESET is taken HIGH. The JTAG interface is able to set PROCREADY to HIGH-Z. ,17 2XWSXW INT interrupt. Indicates the aged or learned queue has at least one entry or a write exception occurred. The service routine should either check the AQUEUE, LQUEUE, and WEX registers, or bits 26-29 of the Address Index register, to determine the cause. The interrupt is cleared after the appropriate flag register has been read and will not be reasserted until either the queue(s) are emptied and then get at least one entry again, or another write exception occurs. The JTAG interface is able to set INT to HIGH-Z. 5(6(7 ,QSXW The /RESET input is used to reset the MUAA RCP. /RESET must be asserted for at least 3 CLK periods. &/. ,QSXW The rising edge of CLK input is the device clock. )) )XOO )ODJ 2XWSXW /FF is active when the device (or chain of devices) is full. /FF becomes inactive when any one device has two open entries. The JTAG interface is able to set /FF to HIGH-Z. &+$,1>@ ,QSXW When two or more devices are chained they communicate among themselves using the CHAIN[3:0] signals. See Chaining section. Internally Pulled-up. &+$,183 2XWSXW When two or more devices are chained they communicate among themselves using the CHAINUP signals. See Chaining section. The JTAG interface is able to set CHAINUP to HIGH-Z. &+$,1'1 2XWSXW When two or more devices are chained they communicate among themselves using the CHAINDN signals. See Chaining section. The JTAG interface is able to set CHAINDOWN to HIGH-Z. &+$,1&6 %LGLUH.WLRQDO When two or more devices are chained they communicate among themselves using the CHAINCS signals. See Chaining section. Internally pulled up. 5HY 2SHUDWLRQDO &KDUD.WHULVWL.V 0) 0DW.K )ODJ 2XWSXW The /MF output indicates whether a match was found. The JTAG interface is able to set /MF to HIGH-Z. 7567 -7$* 5HVHW ,QSXW The /TRST is the Test Reset pin. Internally pulled up with 25K minimum. Must be tied to /RESET or tied LOW when not in use. 7&/. -7$* 7HVW &OR.N ,QSXW The /TCLK input is the Test Clock input. Must be tied at a valid logic level when not in use. 706 -7$* 7HVW 0RGH 6HOH.W ,QSXW The TMS input is the Test Mode Select input. Internally pulled up with 25K minimum. 08$$ 5RXWLQJ &R3UR.HVVRU 5&3 )DPLO\ 7', -7$* 7HVW 'DWD ,QSXW ,QSXW The TDI input is the Test Data input. Internally pulled up with 25K minimum. 7'2 -7$* 7HVW 'DWD 2XWSXW 2XWSXW The TDO output is the Test Data output. 9&& *1' These pins are the power supply connection to the MUAA RCP. VCC must meet the voltage supply requirements in the Operating Conditions section relative to the GND pins, which are at 0 Volts (system reference potential), for correct operation of the device. All the ground and power pins must be connected to their respective planes with adequate bulk and high frequency bypassing capacitors in close proximity to the device. 23(5$7,21$/ &+$5$&7(5,67,&6 /RDGLQJ DQG 8QORDGLQJ In order to keep data alignment simple, the number of words to be loaded and unloaded for each operation is kept consistent for each CAM/RAM partition configuration and the width of the port. Tables 1 and 2 show the cycle sequence and CAM/RAM bit mappings for 32- and 16-bit bus modes. The bus may be selected for each port independently. Table 3 shows whether CAM, RAM or both types of segments are used on input or output cycles for each operation. Loads always start right aligned from the least significant word, CAM partition first, followed by RAM if necessary. Most instructions do not require the entire 80 bits to be loaded. CAM data is required as an input for all operations except READ LQUEUE and READ AQUEUE. The use of RAM data is optional (i.e., it is not necessary to perform all RAM cycles when inputting data). However, the user must be aware that INSERT and LEARN operations will over-write RAM data. Therefore, the application should remain consistent in the number of RAM bits used for these operations. All CAM and RAM segment writes except the last use the LOAD instruction. The last segment of data uses the instruction for the desired operation. Depending on the operation, unloads either start from the right aligned, least significant word of CAM followed by the right aligned, least significant word of RAM or just from the right aligned, least significant word of RAM. For instance, a QUEUE read returns CAM then RAM, whereas a search just returns RAM. Where the CAM/RAM partition does not lie on a port width boundary the last word of the read may contain undefined data in the most significant bits. The number of unload cycles actually completed is optional. The DOUT register stores the results of operations from the asynchronous processor port. Search results are obtained by repeated reads of DOUT until all RAM data is read. When performed from the processor port, READ LQUEUE and READ AQUEUE return the first segment of CAM data on the cycle that requests the operation; additional CAM and RAM segments are obtained by repeated reads of the DOUT register. Loading is flow controlled on the synchronous DIN port with the DINREADY signal, which is HIGH when data is accepted by the DIN port. On the Processor port the PROCREADY signal is HIGH when the current write cycle may complete. 2SHUDWLRQV On the synchronous port, operations are started on the CLK cycle in which the requested Op-Code is written. On the processor port operations are started when the chosen operation register is written. The user should use the flow control mechanisms to determine when results are available. On the synchronous port the /DOUTVALID signal is asserted for one CLK cycle when new data is written to the DOUT port. The processor port will assert its PROCREADY signal on the CLK edge that data is available. Note that there is no internal flow control from the sync DOUT port back to the sync DIN port. The DOUT data is overwritten if it is not unloaded. 5HY 08$$ 5RXWLQJ &R3UR.HVVRU 5&3 )DPLO\ 2SHUDWLRQDO &KDUD.WHULVWL.V 7DEOH %LW %XV 0RGH &$05$0 &\.OHV E\ 3DUWLWLRQ &RQILJXUDWLRQ &\.OH 1R 5$0 &$0 &$0>@ &$0>@ &$0>@ 5$0 &$0 &$0>@ &$0>@ 5$0>@ 5$0 &$0 &$0>@ &$0>@ 5$0>@ 5$0 &$0 &$0>@ 5$0>@ 5$0>@ Note: *Bus bits [15:0] contain data. Bus bits [31:16] are undefined. 7DEOH %LW %XV 0RGH &$05$0 &\.OHV E\ 3DUWLWLRQ &RQILJXUDWLRQ &\.OH 1R 5$0 &$0 &$0>@ &$0>@ &$0>@ &$0>@ &$0>@ 5$0 &$0 &$0>@ &$0>@ &$0>@ &$0>@ 5$0>@ 5$0 &$0 &$0>@ &$0>@ &$0>@ 5$0>@ 5$0>@ 5$0 &$0 &$0>@ &$0>@ 5$0>@ 5$0>@ 5$0>@ 7DEOH ,QSXW DQG 2XWSXW &$05$0 &\.OHV E\ 2SHUDWLRQ 2SHUDWLRQ ,16(57 6($5&+ 6($5&+$ /($51 '(/(7( 5($' /48(8( 5($' $48(8( ',1 352&' :ULWH &$0 5$0 &$0 RQO\ &$0 RQO\ &$0 5$0 &$0 RQO\ 1$ 1$ '287 352&' 5HDG 1$ 5$0 RQO\ 5$0 RQO\ 1$ 1$ &$0 &$0 5$0 5$0 'HYL.H &KDLQLQJ Up to four MUAA RCPs may be chained with no external logic. Figure 3 shows the interconnection. Unused CHAIN[3:0] pins should be left unconnected. The /MF, /FF, INT, DOUTVALID, DINREADY, and PROCREADY signals should only be used on the master device and left disconnected on the slave devices. The master device is the one with no connection to the CHAINUP pin. Where device pins are paralleled, attention should be paid to signal integrity, in particular to signals used for clocking, i.e., CLK, /PCS. PCB layout techniques such as daisy chaining and driver to track impedance matching should be observed. The scheme in Figure 3 allows devices to be designed in but not fitted. The fit order would be MASTER, SLAVE1, SLAVE2, SLAVE3. 5HY 2SHUDWLRQDO &KDUD.WHULVWL.V 08$$ 5RXWLQJ &R3UR.HVVRU 5&3 )DPLO\ ',1 ',1( 23 '287 2( '287( 0$67(5 352&' 352&$ 5: 3&6 &/. 5(6(7 ',1 ',1( 23 '287 2( '287( 352&' 352&$ 5: 3&6 &/. 5(6(7 ',1 ',1( 23 '287 2( '287( 352&' 352&$ 5: 3&6 &/. 5(6(7 ',1 ',1( 23 '287 2( '287( 352&' 352&$ 5: 3&6 &/. 5(6(7 6/$9( 6/$9( 6/$9( ',15($'< '2879$/,' 352&5($'< ,17 )) 0) &+$,1 &+$,1 &+$,1 &+$,1 &+$,1&6 &+$,183 &+$,1'1 &+$,1 &+$,1 &+$,1 &+$,1 &+$,1&6 &+$,183 &+$,1'1 &+$,1 &+$,1 &+$,1 &+$,1 &+$,1&6 &+$,183 &+$,1'1 &+$,1 &+$,1 &+$,1 &+$,1 &+$,1&6 &+$,183 &+$,1'1 )LJXUH 'HYL.H &KDLQLQJ 5HY 08$$ 5RXWLQJ &R3UR.HVVRU 5&3 )DPLO\ 2SHUDWLRQDO &KDUD.WHULVWL.V LQUEUE flags may be set for an entry that has changed status. The user may qualify reads from AQUEUE and LQUEUE with the appropriate ports match flag that will be asserted if the data is valid. ,QWHUUXSWV There are four sources of interrupts that will cause the INT pin to be asserted: AQUEUE, LQUEUE, SWEX, and PWEX. The appropriate enables must be set in the Configuration register to enable the interrupts. The interrupt service routine should read the appropriate flag registers to determine the interrupt cause. The flags are available individually or from the Address Index register. The appropriate individual flag register must be read in order to acknowledge the interrupt. 6:(; DQG 3:(; SWEX and PWEX interrupts are set when a write exception condition occurs. This occurs when two Write cycles are pending in the device and there is only one space left. The SWEX and PWEX flags indicate which port caused the exception and which are available individually to the processor. Both processor write exceptions are available in the processor Address index port and the DOUT port Address index word. /48(8( DQG $48(8( AQUEUE and LQUEUE interrupts are set by an entry being written into one or another of the queues. When the flag register is read the interrupt is acknowledged. The processor may read the LQUEUE and AQUEUE flags to determine when all the entries are read from the appropriate queue. The interrupt will not be reasserted until a queue has been emptied and then gets another entry. Note that it is possible for learned entries to be aged and aged entries to be learned. If this occurs the AQUEUE and 7DEOH -7$* )XQ.WLRQV ,' %LQDU\ . +(; 'HV.ULSWLRQ %LQDU\ . +(; 'HV.ULSWLRQ 9HUVLRQ 9HUVLRQ $ 08$$ $ 08$$ $ . $ . -7$* Refer to IEEE Standard 1149.1 for information on using the JTAG functions. See Table 4 for JTAG functions. BSDL files are available; check the MUSIC Semiconductors website or contact MUSIC Technical Support. -7$* &RGHV 0$18) ,' 0$18) ,' (;7 7(67 %<3$66 6$03/( ,' &2'( &/$03 +,*+= 7\SL.DO ([DPSOH This typical example shows the cycles that the MUAA RCP would perform in a multiport switch. The CAM/RAM partition is set to 48 bits CAM, 32 bits RAM. Both the processor port and the synchronous port are 32 bits wide. The index and flags are programmed to be the last word out of the DOUT port. The synchronous port has priority. The LQUEUE and AQUEUE are enabled. The CAM partition is used to store 48-bit MAC addresses and the RAM partition used to store associated data to the MAC address such as switch port and VLAN numbers. Sync Port Cycle 1 is a search to lookup the port associated with a frame DA (Destination address). At CLK1 the first word (32 bits) of CAM search word is loaded. At CLK2 the last 16 bits of CAM search word is loaded and the instruction "search" given. The most significant 16 bits of the second word are discarded as the CAM partition is 48 bits wide. The results from the DA search will not be available until CLK6 because the operation takes three CLK periods to complete. Due to the internal design of the MUAA RCP, pipelining is possible; therefore, further operations can be performed while the DA search is being done internally. Sync Port cycle2 is a learn on a frame SA (Source address). At CLK3 the first word of CAM is loaded, at CLK4 the second word is loaded (most significant 16 bits discarded). At CLK5 the learn instruction is given along with the word of RAM data that would contain the port ID and other data associated with the SA. At CLK6 the results of the search instruction issued in cycle1 are available at the DOUT bus of the synchronous port, as indicated by /DOUTVALID going active for a CLK. The result of this cycle was a no-match condition as /MF was not asserted LOW. Because the cycle was a DA search and there was a no-match result, there will be no data available on the DOUT bus. Typically in this situation a switch would forward the frame to all ports or all ports on the same VLAN. 5HY 2SHUDWLRQDO &KDUD.WHULVWL.V Sync Port cycle3 starts at CLK8, which is the DA search of the next frame. AT CLK 10 the results of the cycle2 learn operation are available. /MF was not asserted LOW; therefore the 48-bit CAM partition data was not found during the compare. The MUAA RCP automatically writes the 80-bit CAM/RAM word into the next free location of the memory array along with the most up to date time stamp or entry life. The address index is available from the DOUT bus to indicate where in the memory array the data was placed. This can be used to implement further associated data in software or hardware. Furthermore, the INT output is asserted to indicate that the "learned" word was entered into the LQUEUE. Sync Port cycle4, which is the SA learn of the same frame as Sync Port cycle3, is initiated at CLK10. The processor can also be used to access the MUAA RCP for general housekeeping duties. The LQUEUE contains the contents of the virtual learned queue. A processor cycle is started around CLK12 to read the LQUEUE register. This cycle is unable to be completed because the CAM core is busy servicing the synchronous port. PROCREADY remains inactive to inform the processor of the delay. The cycle is therefore extended and will complete when the MUAA RCP asserts PROCREADY HIGH. /MF is asserted LOW to indicate a match result on the CAM partition compare. At this point DOUT will be used to transfer the associated data and the address index of the matching condition. The associated data is available first (RAM partition) and would normally contain the port ID in a typical switch. The RAM partition is configured as 32 bits wide and can therefore be transferred in one CLK period. /DOUTE is asserted by the user to transfer the next word of data on the next clock period. As the RAM takes only one cycle, the address index is available after the associated data. The result of cycle4, which was a SA learn, is available at CLK17. The learn instruction produced a match result. There was no need to overwrite the CAM/RAM partitions, but the MUAA RCP automatically updated the time stamp or entry life of the matching entry. The address index of the entry becomes available at the DOUT port. 08$$ 5RXWLQJ &R3UR.HVVRU 5&3 )DPLO\ The processor cycle data requested earlier, can now become available at CLK21. PROCREADY is asserted HIGH by the device to indicate that the cycle may be completed. The first 32-bit word is available on the PROCD bus and can be read by the processor. The two remaining 32-bit words that complete the LQUEUE entry are read by the subsequent processor cycles. These cycles do not require access to the CAM core, hence the PROCREADY signal is asserted immediately once the cycle is initiated. The processor may use the LQUEUE data to maintain a management database of MAC addresses and associated port IDs. Back to back DA searches are shown from CLK25 onward. This is to demonstrate how the synchronous port handshaking works using the /DINREADY output. Sync port cycle5 and cycle6 are completed normally but at CLK29 /DINREADY goes LOW to indicate that the MUAA RCP cannot accept the load operation of sync cycle7. Therefore the host must hold the DIN, OP, and DINE signals active until /DINREADY goes HIGH. At this point the MUAA RCP will return /DINREADY to HIGH to indicate that it has accepted the DIN and OP information. 5HY &/. ',1( .DP .DP .DP .DP UDP .DP .DP .DP .DP .DP .DP .DP .DP .DP .DP .DP .DP .DP ',1 ORDG VHDU.K ORDG ORDG OHDUQ ORDG VHDU.K ORDG ORDG OHDUQ ORDG VHDU.K ORDG VHDU.K 23 ORDG VHDU.K ORDG VHDU.K 08$$ 5RXWLQJ &R3UR.HVVRU 5&3 )DPLO\ ',15($'< QR PDW.K QR PDW.K PDW.K PDW.K QR PDW.K PDW.K QR PDW.K 0) LQGH[ UDP LQGH[ LQGH[ '287 YDOLG YDOLG YDOLG YDOLG UDP LQGH[ '2879$/,' )LJXUH ([DPSOH 6HTXHQ.H OHDUQ LQ TXHXH .DP OTXHXH OTXHXH DGGU YDOLG YDOLG YDOLG '287( 2( ,17 3&6 OTXHXH .DP OTXHXH UDP 352&' 352&$ OTXHXH DGGU OTXHXH DGGU 5: 2SHUDWLRQDO &KDUD.WHULVWL.V 352&5($'< 5HY ,QVWUX.WLRQ 6HW 'HV.ULSWLRQV 08$$ 5RXWLQJ &R3UR.HVVRU 5&3 )DPLO\ ,16758&7,21 6(7 '(6&5,37,216 0QHPRQL. 1223 %LQDU\ 2S&RGH &/.6 )XQ.WLRQ No operation. 0QHPRQL. ORDG',1! %LQDU\ 2S&RGH &/.6 )XQ.WLRQ Load a word of the DIN data, starting with the least significant word. This instruction is applied to all words loaded into the DIN port except the last word. The last word is loaded with the Op-Code of the operation to be performed. Refer to the Loading and Unloading section. 0QHPRQL. LQVHUW',1! %LQDU\ 2S&RGH &/.6 )XQ.WLRQ Write DIN into the CAM/RAM. If data exists in the CAM partition already, the RAM partition will be overwritten with the new RAM partition data. The entry will be marked as permanent. The address index may be read from the output ports. See Note 1 regarding write exception. 0QHPRQL. VHDU.K',1! %LQDU\ 2S&RGH &/.6 )XQ.WLRQ Search for data in the CAM partition of DIN. If data is found the match flag is asserted and RAM data will appear at DOUT. The address index and flags may also be read. 0QHPRQL. VHDU.KD',1! %LQDU\ 2S&RGH &/.6 )XQ.WLRQ Search for data in the CAM partition of DIN. If data is found the match flag is asserted and RAM data will appear at DOUT and the age of the entry is updated. The address index and flags may also be read. 0QHPRQL. OHDUQ',1! %LQDU\ 2S&RGH &/.6 )XQ.WLRQ Search for data in the CAM partition of DIN. If data is found, the match flag is asserted and the RAM partition written. The address index may be read. Update the age. If data is not found, write the CAM and RAM partitions to the next free address. The address index may be read. See Note 1 regarding write exception. 0QHPRQL. GHOHWH',1! %LQDU\ 2S&RGH &/.6 . . )XQ.WLRQ Search for data on the CAM partition of DIN. If data is found delete the data. The address index may be read. 0QHPRQL. DJH %LQDU\ 2S&RGH &/.6 . . )XQ.WLRQ If the aged virtual queue is disabled: This instruction will remove all entries whose life has expired and are not marked as permanent. Removed entries will not participate in future searches. If the aged virtual queue is enabled: This instruction will move all entries whose life has expired to the aged virtual queue. If a learn instruction matches the CAM partition of an entry in the aged virtual queue, the entry is moved to the learned virtual queue and the new RAM data written. 0QHPRQL. .OHDU %LQDU\ 2S&RGH &/.6 . . )XQ.WLRQ Reset array to empty. 0QHPRQL. .OHDU /48(8( %LQDU\ 2S&RGH &/.6 . . )XQ.WLRQ Delete the contents of the learned virtual queue. The entry will not generate a match on a SEARCH or SEARCHA operation. 0QHPRQL. .OHDU $48(8( %LQDU\ 2S&RGH &/.6 . . )XQ.WLRQ Delete the contents of the aged virtual queue, if enabled. 0QHPRQL. UHDG /48(8( %LQDU\ 2S&RGH &/.6 . . )XQ.WLRQ Read the next learned queue entry. Entries are returned in internal priority order, lowest address first, not in the order they were written. The address index may be read. Note that entries do not have to be read from the LQUEUE if deemed unnecessary. The device treats learned entries as if they are valid entries. 0QHPRQL. UHDG $48(8( %LQDU\ 2S&RGH &/.6 )XQ.WLRQ This instruction is available only if the AQUEUE is enabled. Read the next aged queue entry. Entries are returned in internal priority order, lowest address first, not in the order they were written. The address index may be read. Notes: 1. Due to the pipelined nature of the device, it is possible for a write cycle to be pending (learn or insert) when the device is full. A write exception interrupt will indicate when this occurs if enabled. See Interrupt section. There is one CLK of latency to start the pipe on the synchronous port. The number of CLKs per instruction assumes the pipe is kept full and indicates throughput. 2. 5HY 08$$ 5RXWLQJ &R3UR.HVVRU 5&3 )DPLO\ ,QVWUX.WLRQ 6HW 'HV.ULSWLRQV 3UR.HVVRU 3RUW 5HJLVWHUV 7DEOH 3UR.HVVRU 3RUW 5HJLVWHUV 5HJLVWHU,QVWUX.WLRQ 1223 ORDG',1! LQVHUW',1! VHDU.K',1! VHDU.KD',1! OHDUQ',1! GHOHWH',1! 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